Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture

ABSTRACT

In some embodiments, a fabrication method comprises: forming a structure that has one or more substrates, wherein the one or more substrates are either a single substrate or a plurality of substrates bonded together, wherein the structure comprises a non-electronically-functioning component which includes at least a portion of the one or more substrates and/or is attached to the one or more substrates; wherein the one or more substrates include a first substrate which has: a first side, an opening in the first side, and a conductor in the opening; wherein the method comprises removing material from the structure so that the conductor becomes exposed on a second side of the first substrate. In some embodiments, the second side is a backside of the first substrate, and the exposed conductor provides backside contact pads. In some embodiments, the fabrication method comprises: forming a structure comprising a first substrate which has: a first side, an opening in the first side, and a conductor in the opening; removing material from the structure so that the conductor becomes exposed on a second side of the first substrate; wherein removing of the material comprises removing the material from a first portion of the second side of the first substrate to cause the first portion to be recessed relative to a second portion of the second side of the first substrate.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to devices having substrates withopenings passing through the substrates and conductors in the openings.Some devices of the invention incorporate non-electronically-functioningcomponents. Examples include micro-electro-mechanical systems (MEMS) andother micro-structure-technology (MST) structures.

[0002] Integrated circuit fabrication technology has been used to createmicro-electro-mechanical and micro-electro-optical structures. Examplesof such structures include relays, micropumps, and optical devices forfingerprint recognition. FIG. 1 illustrates one such structure 120formed on a semiconductor die (“chip”) 130. The die contains electroniccircuitry (not shown) and interconnect lines (not shown) which couplethe structure 120 to contact pads 140. The die has been fabricated in abatch process with other such dies on a semiconductor wafer. After thedie was separated from the wafer by dicing, bond wires 150 were bondedto the contact pads 140 and lead frame pins 160. Then the lead frame wasencapsulated into a ceramic substrate 170, with pins 160 protruding fromthe substrate. Another substrate 180 was bonded to substrate 170 toprotect the die and the structure 120. If the structure 120 is anoptical device (e.g. a mirror or an optical sensor), the substrate 180is made of a suitable transparent material, e.g. glass.

[0003] Improved fabrication techniques and structures suitable for suchdevices are desirable. It is also desirable to increase the mechanicalstrength of devices with or without non-electrically functioningcomponents.

SUMMARY

[0004] Some embodiments of the present invention combine techniques forfabricating micro-electro-mechanical and micro-electro-opticalstructures with backside contact fabrication technology used forvertical integration and described in PCT publication WO 98/19337 (TruSiTechnologies, LLC, May 7, 1998).

[0005] The invention is not limited to such embodiments. In someembodiments, a fabrication method comprises:

[0006] forming a structure that has one or more substrates, wherein theone or more substrates are either a single substrate or a plurality ofsubstrates bonded together, wherein the structure comprises anon-electronically-functioning component which includes at least aportion of the one or more substrates and/or is attached to the one ormore substrates;

[0007] wherein the one or more substrates include a first substratewhich has: a first side, an opening in the first side, and a conductorin the opening;

[0008] wherein the method comprises removing material from the structureso that the conductor becomes exposed on a second side of the firstsubstrate.

[0009] In some embodiments, the second side is a backside of the firstsubstrate, and the exposed conductor provides backside contact pads. Thefront side of the first substrate can be bonded to another substrate orsubstrates which protect the non-electronically-functioning componentduring processing, including the processing that exposes the conductor.The component is also protected during dicing. The other substrate orsubstrates can be transparent as needed in the case of an opticalcomponent. The other substrate or substrates can be closely positionedto the component to reduce optical distortion. Also, small system areacan be achieved.

[0010] In some embodiments, the fabrication method comprises:

[0011] forming a structure comprising a first substrate which has: afirst side, an opening in the first side, and a conductor in theopening;

[0012] removing material from the structure so that the conductorbecomes exposed on a second side of the first substrate;

[0013] wherein removing of the material comprises removing the materialfrom a first portion of the second side of the first substrate to causethe first portion to be recessed relative to a second portion of thesecond side of the first substrate.

[0014] The resulting structure may or may not have anon-electronically-functioning component. In some embodiments, the firstsubstrate is thicker at the second portion than at the first portion.The thicker second portion improves the mechanical strength of thestructure.

[0015] Other features and advantages of the invention are describedbelow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a vertical cross-sectional view of a prior art devicehaving a micro-electro-mechanical or micro-electro-optical structure.

[0017]FIGS. 2A, 2B, and 3-16 are vertical cross-sectional views ofdevices with non-electronically-functioning components at differentstages of fabrication according to the present invention.

[0018]FIGS. 17 and 18 are bottom views of devices havingnon-electronically-functioning components according to the presentinvention.

[0019] FIGS. 19-25 are vertical cross-sectional views of devices havingnon-electronically-functioning components at different stages offabrication according to the present invention.

[0020]FIG. 26 is a bottom view of a device withnon-electronically-functioning components according to the presentinvention.

[0021] FIGS. 27-29 are vertical cross-sectional views of devices withnon-electronically-functioning components at different stages offabrication according to the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0022]FIG. 2A illustrates miniature structures 120 fabricated in and/oron a wafer 210. Structures 120 include optical, mechanical, magnetic,and/or other kinds of non-electronically-functioning components.Non-electronically-functioning components may or may not have electroniccircuitry (e.g. transistors), but their operation includes functionalitynot present in traditional electronic circuitry. For example, anon-electronically-functioning component may have to move or deformduring operation. Examples of such components are diaphragms ofmicropumps and moving parts of micro-mechanical switches. The componentmay emit and/or sense visible or invisible light (electromagneticradiation). See J. E. Gulliksen, “MST vs. MEMS: WHERE ARE WE?”,Semiconductor Magazine, Oct. 2000, Vol. 1, No. 10. The component may bea mirror or a lens. Such components may be present in devices forfingerprint recognition, optical disc readers, bar code readers, orother MEMS and MST structures. A component may interact with an externalmagnetic field. The invention is not limited to any particular kind ofcomponents. The invention provides techniques that may be used withcomponents not yet invented.

[0023] The non-electronically-functioning components of structures 120may include parts of substrate 210. The components may also includereleased components, i.e. components originally manufactured on anothersubstrate (not shown) and then released from that substrate. See e.g.U.S. Pat. No. 6,076,256 (released mirrors).

[0024] Structures 120 can be coupled to circuitry 220 fabricated inand/or on substrate 210. Circuitry 220 may be used in operation of thenon-electronically-functioning components. The circuitry may control thecomponents or receive signals indicative of the state of the components.Circuitry 220 may include amplifiers, filters, or any other electroniccircuitry. Substrate 210 can be made from a suitable semiconductormaterial, for example, silicon. In some embodiments, circuitry 220contains only interconnect lines. In some of these embodiments,substrate 210 is made from a non-semiconductor material, for example, adielectric polymer or glass.

[0025] Circuitry 220 and/or structures 120 are connected to contactstructures 230. One structure 230 is shown on a larger scale in FIG. 2B.Structures 230 can be fabricated as described, for example, in PCTpublication WO 98/19337 (TruSi Technologies, LLC, May 7, 1998); U.S.application Ser. No. 09/083,927, filed May 22, 1998; and U.S.application Ser. No. 09/456,225, filed Dec. 6, 1999; all of which areincorporated herein by reference. Briefly, vias 260 are etched insubstrate 210. Insulator 270 is formed in the vias. Conductor 280 (forexample, metal) is formed over the insulator 270. Optionally, anothermaterial 290 is formed over the conductor 280 to fill the vias.

[0026] Insulator 270 can be omitted if wafer 210 is made from aninsulating material. Also, the vias can be filled with conductor 280.

[0027] Structures 120, circuitry 220, and contact structures 230 can befabricated in any order. For example, circuitry 220 can be made first,contact structures 230 can be made next, and the structures 120 can bemade last. Alternatively, the steps forming the elements 230, 220, 120can be interleaved, and the same steps can be used to form more than oneof these elements.

[0028]FIG. 3 shows a wafer 310 which will be bonded to wafer 210.Cavities 320 have been formed in the wafer. Alignment marks (not shown)can be formed on substrate 310 on the same or opposite side as cavities320. In one embodiment, wafer 310 is glass polished on top and bottom.In some embodiments, wafers 310 and 210 are made of the same material(for example, silicon) to match their thermal expansion coefficients.

[0029] Cavities 320 and the alignment marks can be formed byconventional processes. See for example, U.S. Pat. No. 6,097,140 (glassetch).

[0030] Wafers 310, 210 are bonded together (FIG. 4). Structures 120become positioned in cavities 320. The wafers can be bonded byconventional techniques, for example, with an adhesive or a glass fritin vacuum. Before the adhesive is deposited, and even before thestructures 120 are attached to wafer 210, portions of wafer 210 can becovered with an insulating material to insulate the wafer from theadhesive.

[0031] The wafers can also be bonded by solder bonding, eutecticbonding, thermocompression, with epoxy, and by other techniques, knownor to be invented.

[0032] Then the backside 210B of wafer 210 (the side opposite to theside bonded to wafer 310) is processed to expose the contacts 280Cformed by the conductor 280 at the bottom of vias 260. This processingcan be performed by methods described in U.S. patent application Ser.No. 09/456,225 and PCT application WO 98/19337. According to one suchmethod, substrate 210 and insulator 270 are etched by an atmosphericpressure plasma etch to expose the contacts 280C. Then an insulator 520(FIG. 6) is grown selectively on silicon 210 but not on conductor 280.

[0033] According to another method, after the conductor 280 has beenexposed by the etch of substrate 210 and insulator 270, the structure isturned upside down (FIG. 7), and insulator 520 is deposited by a spin-onor spraying process and then cured. Insulator 520 can be polyimide,glass, or some other flowable material (for example, a flowablethermosetting polymer.) The top surface of layer 520 is substantiallyplanar, or at any rate the layer 520 is thinner over contact structures230 than elsewhere. In some embodiments, layer 520 does not cover thecontacts 280C. If needed, layer 520 can be etched with a blanket etch toadequately expose the contacts 280C (e.g., if insulator 520 covered thecontacts). The etch does not expose the substrate 210. The resultingwafer structure is like that of FIG. 5.

[0034] According to another method, the etch of substrate 210 exposesthe insulator 270 but not the conductor 280. See FIG. 8. Insulator 270protrudes from the substrate surface. The wafer structure is turnedupside down (FIG. 8), and insulating layer 520 is formed as describedabove in connection with FIG. 7. Layer 520 is thinner over the contactstructures 230 than elsewhere. In some embodiments, layer 520 does notcover the contact structures. If needed, layer 520 can be etched with ablanket etch to adequately expose the insulator 270 (FIG. 9). Theninsulator 270 is etched selectively to insulator 520 to expose theconductor 280. In some embodiments, insulator 270 is silicon dioxide andinsulator 520 is polyimide. The resulting wafer structure is like thatof FIG. 6.

[0035] One advantage of the processes of FIGS. 5-9 is that nophotolithography is required. Other techniques, including techniquesinvolving photolithography, can also be used.

[0036] The wafer structure is diced into individual chips 1010 (FIG.10). The structures 120 are protected by the substrates 210, 310 duringdicing.

[0037] Chips 1010 can be attached to a wiring substrate (not shown), forexample, a printed circuit board (PCB). Contacts 280C can be directlyattached to the wiring substrate using flip chip technology. See theaforementioned U.S. patent application Ser. No. 09/456,225.Alternatively, chips 1010 can be turned upside down, with the contacts280C facing up, and the chips can be wire bonded to a lead frame andpackaged using conventional technology. Ball grid arrays, chip scalepackages, and other packaging technologies, known or to be invented, canbe used.

[0038] Advantageously, after wafers 210, 310 have been bonded together,the structures 120 and circuitry 220 are protected by the two wafers.The area is small because the substrate 310 does not extend around thesubstrate 210 as in FIG. 1. Cavities 320 can be made shallow so that thesubstrate 310 can be positioned close to structures 120. This isadvantageous for optical applications because optical distortion isreduced. Further, since substrate 310 is placed directly on substrate210, precise positioning of substrate 310 relative to structures 120 isfacilitated.

[0039] For optical applications, substrate 310 can be covered bynon-reflective coatings. Cavities 320 can be filled with refractiveindex matching materials. Lenses can be etched in substrate 310.

[0040] Substrate 310 may contain electronic circuitry coupled tostructures 120 and/or circuitry 220. Substrate 310 can be fabricatedfrom insulating or semiconductor materials. U.S. patent application Ser.No. 09/456,225 describes some techniques that can be used to connectcircuitry in substrate 310 to circuitry 220.

[0041]FIG. 11 illustrates an embodiment in which the backside contactsare redistributed along the backside 210B of wafer 210 to obtain an areamatched package. After the stage of FIG. 4, mask 1110 is formed on thebackside 210B of substrate 210 and photolithographically patterned.Optionally, before the mask is formed, substrate 210 can be thinned frombackside 210B, but the insulator 270 does not have to be exposed. Thethinning can be performed by mechanical grinding, plasma etching, orother methods, known or to be invented.

[0042] Substrate 210 and insulator 270 are etched selectively to mask1110 to expose contact portions 280C of conductor 280 on backside 210B(FIG. 12). Suitable etching processes are described above in connectionwith FIG. 5. Then mask 1110 is stripped, and insulating layer 520 (FIG.13) is formed selectively on backside 210B of substrate 210 but not onconductor 280. See the description above in connection with FIG. 6.

[0043] Conductive layer 1410 (FIG. 14), for example, a metal suitablefor integrated circuit bond pads, is deposited and patterned on thewafer backside to provide conductive pads 1410C and conductive linesconnecting these pads to conductor 280. Then a suitable insulator 1510(FIG. 15) is deposited and patterned to expose the conductive pads1410C.

[0044] Then the wafer structure is diced (FIG. 16). Pads 1410C of theresulting chips 1010 can be attached directly to a wiring substrate, forexample, a PCB. The bottom view of a single chip 1010 is shown in FIG.17. FIG. 17 also shows an outline of mask 1110 of FIG. 11.

[0045] One advantage of the embodiment of FIGS. 11-17 is as follows. Theposition of contact structures 230 is limited by the layout of circuitry220 and structures 120. For example, the contact structures 230 may haveto be restricted to the periphery of chips 1010. Since contacts 280C arenot directly attached to a wiring substrate, their size can be reduced.The size of contact pads 1410C is sufficiently large to allow directattachment to a wiring substrate, but the position of contact pads 1410Cis not restricted by circuitry 220 and structures 120. The chip area cantherefore be smaller.

[0046] In FIG. 18, the mask 1110 has four extensions 1110E extending tothe boundary (e.g. corners) of chip 1010. These extensions increase themechanical strength of the chip. The extensions may come as close, orcloser, to the chip boundary as the contacts 280C. In some embodiments,the extensions reach the chip boundary and merge with the extensions onthe adjacent chips. The extensions may extend between the contacts. Moreor fewer than four extensions can be provided.

[0047] The extensions can be formed in structures that do not havenon-electronically-functioning components.

[0048] In another embodiment, the wafer structure is processed to thestage of FIG. 6 by any of the methods described above in connection withFIGS. 5-9. Then conductive layer 1410 (FIG. 19) is deposited andpatterned on backside 210B over insulator 520 to form contact pads 1410Cand conductive lines connecting the contact pads to conductor 280, asdescribed above in connection with FIG. 14. Mask 1110 is not used. Theninsulator 1510 is deposited and patterned to expose the contact pads1410C, as described above in connection with FIG. 15.

[0049] The wafer structure is tested and diced to form individual chips1010 (FIG. 20).

[0050]FIG. 21 illustrates alternative processing of wafer 310. Nocavities are etched in the wafer. Stand-off features 2110 are formed onthe wafer surface. Features 2110 can be formed by depositing anappropriate material and patterning the material photolithographically,or by silk-screen printing, or by dispensing the material using aneedle, or by other techniques, known or to be invented. Suitablematerials include epoxy, thermosetting polymers, glass frit.

[0051] Wafer 210 is processed as in FIG. 3. Then wafers 310, 210 arealigned and bonded as shown in FIG. 22. Stand-off features 2110 arebonded to wafer 210. Structures 120 are located between the stand-offfeatures. Then the wafer structure is processed by any of the methodsdescribed above in connection with FIGS. 5-20.

[0052] In the embodiment of FIG. 22, material 2110 is used to fill thevias 260. Material 290 that fills the vias in FIG. 2B is absent in FIG.22, or is used to fill the vias only partially. Material 2110 is notfully hardened when the wafers are bonded. Material 2110 fills the vias260 during the bonding process. The bonding is performed in vacuum tomake it easier for the material 2110 to fill the vias 260.

[0053] In some embodiments in which the bonding process starts beforethe material 2110 is hardened, spacers are formed on wafer 310 or 210,or both, to maintain a minimum distance between the two wafers toprevent the wafer 210 from damaging the structures 120. The spacers canbe fixed hard features formed on the wafers. Alternatively, the spacerscan be hard balls 2120 floating in material 2110. The balls can be madeof glass, resin, or some other suitable material (possibly adielectric). Balls 2120 maintain the minimum distance between the wafers310, 210 when the wafers are bonded together. An exemplary diameter ofballs 2120 is 10-30 μm. The diameter is determined by the distance to bemaintained between the two wafers. See U.S. Pat. No. 6,094,244, issuedJul. 25, 2000.

[0054] In some embodiments, the stand-off features 2110 completelysurround the structures 120 and maintain the vacuum in the regions inwhich the structures 120 are located. The vacuum helps to hermeticallyisolate the structures 120 when the ambient pressure increases toatmospheric pressure. The strength of the bond between the two wafers isalso improved.

[0055] In some embodiments, the material 2110 is deposited on wafer 210rather than wafer 310.

[0056] In some embodiments, the material 2110 covers and contacts thestructures 120.

[0057] In some embodiments, the material 2110 is hardened before thewafers are bonded, and is not used to fill the vias 260.

[0058] In FIG. 23, structures 120 do not protrude from the top surfaceof substrate 210. No cavities or stand-off features are made on wafer310. This provides close positioning between the substrate 310 andstructures 120. This is particularly advantageous if the structures 120have optical components.

[0059] In FIGS. 24-26, at least some of the contact structures 230 arepositioned on the chip boundaries (on the dicing lines). In otherrespects, fabrication can proceed according to any method describedabove in connection with FIGS. 5-23. FIG. 24 illustrates the waferstructure processed as in FIG. 4. FIG. 25 illustrates the structureafter dicing. FIG. 26 is a bottom view of a resulting chip 1010. Oneadvantage of placing the contact structures 230 on the chip boundariesis reduced area. Also, the contact structures 230 can be contacted on aside of the chip, especially if the material 290 is conductive or isomitted. If the wafer structure is processed as in FIGS. 16 or 20,contacts 1410C are available on the backside while contact structures230 can be contacted on the sides. In some embodiments, the large widthof vias 260 in which the contact structures are formed allows the viasto be etched by an isotropic etching process. Isotropic etching can beless expensive than anisotropic etching.

[0060] In some embodiments, the vias 260 are filled with material 2110,as in FIG. 22.

[0061] In FIGS. 24-26, the wafer 310 is as in FIG. 21. In otherembodiments with contact structures 230 on the chip boundaries, wafer310 is as in FIGS. 3 or 23.

[0062] In FIG. 27, cavities 2710 have been formed in wafer 310 on thetop side along the dicing lines. Cavities 2710 can be formed before orafter the wafers 310, 210 are bonded together. Cavities 2710 can extendthe whole length of the dicing lines, or can be scattered along thedicing lines in any pattern. FIG. 28 shows the structure after dicing.Cavities 2710 reduce the stress during dicing and also reduce the timethat the structure is exposed to the stress. The dicing damage istherefore less. This is particularly advantageous if substrate 310 is atransparent substrate used for optical purposes, since damage tosubstrate 310 can cause optical distortion.

[0063] Cavities 2710 can be used in conjunction with any of thestructures and processes described above in connection with FIGS. 2-26.

[0064] Structures 120 can be manufactured using multiple wafers. In theexample of FIG. 29, structures 120 include portions of wafer 210 and ofwafers 2904 bonded to the front side of wafer 210. Examples of suchstructures include micropumps. See for example U.S. Pat. No. 6,116,863issued Sep. 12, 2000, entitled “Electromagnetically Driven MicroactuatedDevice and Method of Making the Same”. In FIG. 29, passages 2910 inwafer 310 represent the pumps' inlets and outlets. During fabrication,the wafers 2904 and the front side of wafer 210 are processed as neededto manufacturer the structures 120. Wafers 210, 2904 are bondedtogether. Wafer 310 is processed as needed (for example, to formcavities 320 of FIG. 3, or stand-off features 2110 of FIG. 24, orpassages 2910). Then wafer 310 is bonded to the top wafer 2904. Afterthat, fabrication proceeds as described above in connection with FIGS.4-28. The backside of wafer 210 is processed to expose the contactstructures 230. The wafer backside in FIG. 29 is as in FIG. 19, butother processes described above can also be used. FIG. 29 shows thestructure after dicing.

[0065] The embodiments described above illustrate but do not limit theinvention. The invention is not limited to any particular materials,processes, dimensions, layouts, or to any particular types of structures120. Structures 120 may have mechanical components, that is, componentsthat move during operation. Other embodiments and variations are withinthe scope of the invention, as defined by the appended claims.

What is claimed is:
 1. A fabrication method comprising: forming astructure that has one or more substrates, wherein the one or moresubstrates are either a single substrate or a plurality of substratesbonded together, wherein the structure comprises anon-electronically-functioning component which includes at least aportion of the one or more substrates and/or is attached to the one ormore substrates; wherein the one or more substrates include a firstsubstrate which has: a first side, an opening in the first side, and aconductor in the opening; wherein the method comprises removing materialfrom the structure so that the conductor becomes exposed on a secondside of the first substrate.
 2. The method of claim 1 wherein theconductor in the opening is part of a circuit formed in the one or moresubstrates and used in operation of the non-electronically-functioningcomponent.
 3. The method of claim 1 wherein the one or more substratesare a plurality of substrates bonded together.
 4. The method of claim 3wherein forming the structure comprises: forming a stand-off feature ona substrate S1 which is one of said substrates, the feature standing offon the substrate S1; and bonding the substrates together so that thestand-off feature is positioned between the substrate S1 and anothersubstrate S2 which is one of the substrates, wherein the first substrateis one of the substrates S1 and S2.
 5. The method of claim 4 wherein thematerial from which the stand-off feature is made fills the opening atleast partially.
 6. The method of claim 5 wherein the bonding of thesubstrate S1 to the substrate S2 is performed before the material of thestand-off feature is hardened, the material of the stand-off featureflowing into the opening during this bonding.
 7. The method of claim 4further comprising a spacer made on the substrate S1 or S2, to maintaina minimum distance between the substrates S1 and S2 and thus protect thenon-electronically-functioning component at least part of which ispositioned between the substrates S1 and S2.
 8. The method of claim 7wherein the bonding of the substrate S1 to the substrate S2 is performedbefore material of the stand-off feature is hardened, and the spacercomprises hard substance in the non-hardened material of the stand-offfeature.
 9. The method of claim 1 wherein removing of the materialcomprises removing the material from a first portion of the second sideof the first substrate to cause the first portion to be recessedrelative to a second portion of the second side of the first substrate.10. The method of claim 9 wherein: the structure is to provide a chip;the opening is positioned adjacent to a boundary of said chip; and thesecond portion comprises a part extending towards the boundary of saidchip.
 11. The method of claim 10 wherein: the first substrate has aplurality of openings in the first side, and a conductor in each of theopenings; removing of the material exposes the conductor on the secondside in each of the openings; the part extending towards the boundary ofthe chip extends between the openings.
 12. The method of claim 10wherein the part extending towards the boundary reaches the boundary ofthe chip.
 13. The method of claim 10 wherein the part extending towardsthe boundary comes at least as close to the boundary as the exposedconductor on the second side.
 14. The method of claim 10 wherein thepart extends towards a corner of the chip.
 15. The method of claim 9further comprising forming, over the second side, one or moreinterconnect lines which extend from the exposed conductor to the secondportion, and forming an insulator overlaying the conductor on the secondside but exposing a contact on the second portion, the contact beingelectrically connected to the conductor by one or more of theinterconnect lines.
 16. The method of claim 3 further comprising dicingthe structure after the conductor has been exposed on the second side.17. The method of claim 3 wherein the plurality of substrates comprisesa second substrate which at least partially protects thenon-electronically-functioning component during said removing ofmaterial from the structure.
 18. The method of claim 1 furthercomprising attaching the conductor's surface exposed on the second sideto a wiring substrate.
 19. The method of claim 1 wherein the second sideis opposite from the first side.
 20. The method of claim 1 wherein thefirst substrate is a semiconductor substrate.
 21. The method of claim 20wherein: the opening contains a first insulator insulating the conductorfrom sidewalls of the opening; and removing the material from thestructure comprises: (A) removing semiconductor material from the secondside to expose the first insulator; and (B) removing the first insulatoron the second side to expose the conductor.
 22. The method of claim 21further comprising forming a second insulator over the semiconductormaterial on the second side, the second insulator not completelycovering the conductor on the second side.
 23. The method of claim 22wherein the second insulator is formed after the operation (B).
 24. Themethod of claim 22 wherein the second insulator is formed after theoperation (A) but before the conductor is exposed by the operation (B).25. The method of claim 22 wherein forming the second insulatorcomprises: forming the second insulator over the semiconductor materialand over the conductor; and etching the second insulator with a blanketetch to completely remove the second insulator over at least a portionof the conductor but not completely remove the second insulator over thesemiconductor material.
 26. The method of claim 20 further comprisingforming an insulator over the semiconductor material on the second side,the insulator not completely covering the conductor on the second side.27. The method of claim 1 wherein: the opening is one or a plurality ofopenings in the first side, each of the openings containing a conductorfor carrying an electrical signal; and the operation of removingmaterial from the second side causes the conductors to be exposed in theopenings.
 28. The method of claim 1 wherein operation of thenon-electronically-functioning component requires the component to beable to (a) move or deform; and/or (b) emit, sense, or otherwiseinteract with electromagnetic radiation.
 29. A device comprising: astructure that has one or more substrates, wherein the one or moresubstrates are either a single substrate or a plurality of substratesbonded together, wherein the structure comprises anon-electronically-functioning component which includes at least aportion of the one or more substrates and/or is attached to the one ormore substrates; wherein the one or more substrates include a firstsubstrate which has a first side, a second side, an opening passingthrough the first substrate from the first side to the second side, andthe device comprises a conductor in the opening, the conductor beingexposed on the second side.
 30. The device of claim 29 wherein theconductor in the opening is part of a circuit formed in the one or moresubstrates and used in operation of the non-electronically-functioningcomponent.
 31. The device of claim 29 wherein the one or more substratesare a plurality of substrates bonded together.
 32. The device of claim31 wherein the structure comprises a stand-off feature betweensubstrates S1 and S2 which are two of said substrates, the firstsubstrate being one of the substrates S1 and S2.
 33. The device of claim32 wherein the material from which the stand-off feature is made fillsthe opening at least partially.
 34. The device of claim 32 furthercomprising a spacer made on the substrate S1 or S2.
 35. The device ofclaim 34 wherein the spacer comprises a glass or resin ball embeddedinto the stand-off feature.
 36. The device of claim 29 wherein theconductor is exposed at a first portion of the second side, and thesecond side has a second portion protruding from the second siderelative to the first portion.
 37. The device of claim 36 wherein: theopening is positioned adjacent to a boundary of the structure; and thesecond portion comprises a part extending towards the boundary of thestructure.
 38. The device of claim 37 wherein: the first substrate has aplurality of openings passing from the first side to the second side,and a conductor in each of the openings; the part extending towards theboundary of the structure extends between the openings.
 39. The deviceof claim 37 wherein the part extending towards the boundary comes atleast as close to the boundary as the opening.
 40. The device of claim37 wherein the part extending towards the boundary comes at least asclose to the boundary as the exposed conductor on the second side. 41.The device of claim 37 wherein the part reaches a corner of thestructure.
 42. The device of claim 36 further comprising: one or moreinterconnect lines which overlay the second side and extend from theexposed conductor on the second side to the second portion; and aninsulator overlaying the conductor on the second side but exposing acontact on the second portion, the contact being electrically connectedto the conductor by one or more of the interconnect lines.
 43. Thedevice of claim 29 in combination with a wiring substrate attached tothe conductor's surface exposed on the second side.
 44. The device ofclaim 29 wherein the second side is opposite from the first side. 45.The device of claim 29 wherein the first substrate is a semiconductorsubstrate.
 46. The device of claim 45 wherein the opening contains afirst insulator insulating the conductor from sidewalls of the opening.47. The device of claim 46 further comprising a second insulator formedover the semiconductor material on the second side, the second insulatornot completely covering the conductor on the second side.
 48. The deviceof claim 45 further comprising an insulator formed over thesemiconductor material on the second side, said insulator not completelycovering the conductor on the second side.
 49. The device of claim 29wherein the opening is one or a plurality of openings each of whichpasses through the first substrate from the first side to the secondside, and the device comprising a conductor in each of the openings, theconductor being exposed on the second side.
 50. The device of claim 29wherein operation of the non-electronically-functioning componentrequires the component to be able to (a) move or deform; and/or (b)emit, sense, or otherwise interact with electromagnetic radiation.
 51. Afabrication method comprising: forming a structure comprising a firstsubstrate which has: a first side, an opening in the first side, and aconductor in the opening; removing material from the structure so thatthe conductor becomes exposed on a second side of the first substrate;wherein removing of the material comprises removing the material from afirst portion of the second side of the first substrate to cause thefirst portion to be recessed relative to a second portion of the secondside of the first substrate.
 52. The method of claim 51 wherein: thestructure is to provide a chip; the opening is positioned adjacent to aboundary of said chip; and the second portion comprises a part extendingtowards the boundary of said chip.
 53. The method of claim 52 wherein:the first substrate has a plurality of openings in the first side, and aconductor in each of the openings; removing of the material exposes theconductor on the second side in each of the openings; the part extendingtowards the boundary of the chip extends between the openings.
 54. Themethod of claim 52 wherein the part extending towards the boundary comesat least as close to the boundary as the opening.
 55. The method ofclaim 42 wherein the part extending towards the boundary reaches theboundary.
 56. The method of claim 42 wherein the part reaches a cornerof the chip.
 57. The method of claim 51 further comprising forming, overthe second side, one or more interconnect lines which extend from theexposed conductor to the second portion, and forming an insulatoroverlaying the conductor on the second side but exposing a contact onthe second portion, the contact being electrically connected to theconductor by one or more of the interconnect lines.
 58. The method ofclaim 51 wherein the first substrate is a semiconductor substrate. 59.The method of claim 58 wherein: the opening contains a first insulatorinsulating the conductor from sidewalls of the opening; and removing thematerial from the structure comprises: (A) removing semiconductormaterial from the second side to expose the first insulator; and (B)removing the first insulator on the second side to expose the conductor.60. The method of claim 59 further comprising forming a second insulatorover the semiconductor material on the second side, the second insulatornot completely covering the conductor on the second side.
 61. A devicecomprising: a structure comprising a first substrate which has a firstside, a second side, an opening passing through the first substrate fromthe first side to the second side, and a conductor in the opening, theconductor being exposed on the second side; wherein the conductor isexposed at a first portion of the second side, and the second side has asecond portion protruding from the second side relative to the firstportion.
 62. The device of claim 61 wherein: the opening is positionedadjacent to a boundary of the structure; and the second portioncomprises a part extending towards the boundary of the structure. 63.The device of claim 62 wherein: the first substrate has a plurality ofopenings passing from the first side to the second side, and a conductorin each of the openings; the part extending towards the boundary of thestructure extends between the openings.
 64. The device of claim 62wherein the part extending towards the boundary reaches the boundary.65. The device of claim 62 wherein the part extending to the boundarycomes at least as close to the boundary as the exposed conductor on thesecond side.
 66. The device of claim 62 wherein the part reaches acorner of the structure.
 67. The device of claim 61 further comprising:one or more interconnect lines which extend from the exposed conductoron the second side to the second portion; and an insulator overlayingthe conductor on the second side but exposing a contact on the secondportion, the contact being electrically connected to the conductor byone or more of the interconnect lines.
 68. The device of claim 51wherein the first substrate is a semiconductor substrate.
 69. The deviceof claim 68 wherein the opening contains a first insulator insulatingthe conductor from sidewalls of the opening.
 70. The device of claim 69further comprising a second insulator formed over the semiconductormaterial on the second side, the second insulator not completelycovering the conductor on the second side.
 71. The device of claim 68further comprising an insulator formed over the semiconductor materialon the second side, said insulator not completely covering the conductoron the second side.